A current challenge of the field of integrated circuit (IC) design and manufacturing is how to reduce resistive capacitive delays of signal transmissions. A plurality of methods have been developed. One is substituting aluminum metal layers with copper metal layers to reduce serial resistances between the metal layers. Another is reducing parasite capacitances between metal layers, which may be achieved by forming porous low dielectric constant (low-K) materials or air gaps in dielectric layers between the metal layers.
FIG. 1 illustrates an excising interconnection structure. The interconnection structure includes: a substrate 5 having semiconductor devices (not shown) inside; a low-K dielectric layer 4 on the semiconductor substrate 5; a mask layer 6 on the low-K dielectric layer 4; through holes (not shown) formed by patterning the low-K dielectric layer 4 through the mask layer 6; and connection vias (not shown) electrically connected with the semiconductor devices formed by filling the through holes with metal materials.
However, a via miss defect may be easily formed when the low-K dielectric layer 4 is patterned using the mask layer 6 as a patterning mask. The via miss defect may refer to the structure where the vias are not able to completely penetrate through the low-K dielectric layer 4, or even worse, no via is formed.
The via miss defect may affect a yield of the interconnection structure, and may also affect the reliability of an electrical connection of the interconnection structure. The disclosed methods and systems are directed to solve one or more problems set forth above and other problems.